Custom hardware modules are implemented in the FPGA, providing a glue layer between the application processors and RF Transceiver. Combined with a field programmable gate array (FPGA). Featuring two ARM Cortex A9 application processors running at 667Mhz. The latest ADALM-PLUTO revision D units contain a Zynq 7Z010. Allowing it to accept and provide a stream of IQ samples representing the radio signal being transmitted or received by the Zynq SoC at the user’s configured sample rate. The AD9363 contains the necessary amplifiers and filters, along with digital to analog and analog to digital converters. The two main components are the Analog AD9363 RF Transceiver and Xilinx Zynq 7000 Series System on Chip (SoC). The ADALM-PLUTO features the following architecture: Analog ADALM-PLUTO Architecture. As such Analog provide a vast amount of high quality documentation on every aspect of the platform, accessible through their Wiki. The Analog ADALM-PLUTO is part of Analog’s active learning module family of low cost development boards aimed at those wishing to learn and experiment with software defined radios (SDRs). If you’re just interested in trying and don’t care too much about the long and arduous journey or ADALM-PLUTO’s internals, skip ahead to Booting / Upgrade. With all the various components in line, it then becomes a simple case of configuring srsRAN to use the ADALM-PLUTO as its RF interface and throwing the switch. Finally updating the host PC’s ADALM-PLUTO module, part of the SoapySDR driver, exposing the new timestamp support to applications. I then implement a new system service to communicate with the host PC running srsRAN. I take a slightly lighter touch approach than the SRS team, adding a pair of hardware blocks to implement the functionality. Using a dash of inspiration from srsRAN’s implementation, I produce my own version of the HDL code. This post covers implementing my own timestamping solution, specifically for the ADALM-PLUTO. While the network would occasionally appear to be visible to the mobile device any attempts to register with it would be met with a barrage of errors from the eNodeB application. It seemed that the ADALM-PLUTO simply wasn’t able to keep up or stay in sync with the PC. Having initially given the released build a go I was hopeful however found that not all was well. They even produced a build of their updated hardware descriptor language code (HDL) specifically for the ADALM-PLUTO, which can be loaded on top of the stock Analog firmware. The srsRAN team implemented the missing timestamping functionality recently, targeting boards which use similar architectures, consisting of a Xilinx Zynq paired with an Analog RF Transceiver. Initially the answer was no, as there was no support for the transmit and receive timestamping required by LTE. Having bumped into the Analog ADALM-PLUTO some time a go I wondered if it could be used for LTE simulation. While the LimeSDR is great value for money considering its performance, it’s overkill for testing the IoT devices I’ve been working on recently. Since then I’ve been considering even lower cost and more readily available options. Previously I got the open source LTE stack srsRAN working with the low cost LimeSDR.
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